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BrightSpots 3D IC 2
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Moderator: Robert Petrossian , Francoise Von Trapp
8 topics, 42 replies
26353 07/20/2009 9:19am
Developments in methodologies for 3D integration schemes using TSV interconnect have been moving forward at a good pace, however there are still areas to be addressed. This forum will address both the progress being made thus far, and the roadblocks yet to be addressed.
Moderator: Robert Petrossian , Francoise Von Trapp
5 topics, 18 replies
15043 07/20/2009 9:12am
Establishing a supply chain infrastructure to accommodate 3D integration using TSVs has been identified as one of the most immediate issues needing to be addressed. This forum will discuss the industry options, and what's being done about it.
Moderator: Robert Petrossian , Francoise Von Trapp
3 topics, 12 replies
7363 07/09/2009 11:01am
Standards for 3D IC integration -- are they necessary for market adoption and how will they come about? This forum will address these questions.
Moderator: Robert Petrossian , Ed Korczynski
7 topics, 13 replies
20497 07/09/2009 11:10am
This is an extended discussion from the Taller vs. Smaller panel discussion held July 1 at the 2009 Lithography Workshop.
By Gerry Geronimo on Sep. 13, 2011 - 0 reply
2020 No replies yet
11 members contributed, 24 topics and 85 replies in 4 forums.
 
 
 

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By Gerry Geronimo On Sep. 13, 2011
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By Francoise Von Trapp On Jul. 20, 2009
Existing pick-and-place/die bonding tools can either achieve speed, or accuracy in alignment required for D2D stacking, but not both. How is this being addressed? Sitaram - are there any plans at SEMATECH to address this issue? Read More>>
By Francoise Von Trapp On Jul. 20, 2009
I'm not sure if this question falls under supply chain or technology development, but as we all know, making 3D IC with TSV interconnects cost effective is one of the keys to market adoption. How can synergies in the various unit processes be exploited to help drive down costs? Read More>>
By Francoise Von Trapp On Jul. 09, 2009
Ric - what types of simulation capabilities do we feel are necessary to support 3D IC process development? Has Synopsys been working on tools to address these needs? Read More>>
By Francoise Von Trapp On Jul. 09, 2009
Contact issues, known good die, and quality assurance have all been identified as test issues that need to be addressed with 3D ICs.  Bob and/or Sitaram,  can you offer your perspective on how 3D ICs should be tested, and what difficulties does this present? Read More>>
By Ed Korczynski On Jul. 09, 2009
With separate 2D roadmaps already needed for Logic, DRAM, and Flash, will divergent IC applications call for multiple 3D roadmaps (perhaps global vs. local interconnect, memory-stack vs. SoC, etc.)? Read More>>
By Francoise Von Trapp On Jul. 09, 2009
Paul, in your opinion as an equipment manufacturer, what has been delaying the implementation of 3D IC technology in high-volume manufacturing? Read More>>
By Francoise Von Trapp On Jul. 09, 2009
Will alternative interconnect technologies like Vertical Circuits Vertical Interconnect Pillars, or 3D Plus’s  WDoD (wire-free die-on-die) technology based on “known rebuilt good wafers’ affect market adoption of  TSV stacked ICS?  Why or why not? Read More>>
By Ed Korczynski On Jul. 09, 2009
The Lithography Workshop started in 1981 to try to break the “one-micron optical barrier,” so a limit has always been seen on the horizon. However, through i193 lithography, the science was already known so that we only had to solve engineering problems with incredible dilligence; can we really predict the costs and milestones of developing EUV and other NGL technologies that rely upon unpredictable scientific breakthroughs? Read More>>
By Francoise Von Trapp On Jul. 09, 2009
Welcome to the first day of the 3D Brightspots IC forum. This first round of questions across the topics is directed to all the panelists. Are standards necessary for the adoption of 3D integration schemes? Read More>>