By Gerry Geronimo On Sep. 13, 2011
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By Francoise Von Trapp On Jul. 20, 2009
Existing pick-and-place/die bonding tools can either achieve speed, or accuracy in alignment required for D2D stacking, but not both. How is this being addressed? Sitaram - are there any plans at SEMATECH to address this issue? Read More>>
By Francoise Von Trapp On Jul. 20, 2009
I'm not sure if this question falls under supply chain or technology development, but as we all know, making 3D IC with TSV interconnects cost effective is one of the keys to market adoption. How can synergies in the various unit processes be exploited to help drive down costs? Read More>>
By Francoise Von Trapp On Jul. 09, 2009
Ric - what types of simulation capabilities do we feel are necessary to support 3D IC process development? Has Synopsys been working on tools to address these needs? Read More>>
By Francoise Von Trapp On Jul. 09, 2009
Contact issues, known good die, and quality assurance have all been identified as test issues that need to be addressed with 3D ICs.  Bob and/or Sitaram,  can you offer your perspective on how 3D ICs should be tested, and what difficulties does this present? Read More>>