By Francoise Von Trapp On Jul. 06, 2009
In his recent blog post on Semiconductor International, Dick James talks about SanDisk’s success with stacking 9 chips in a microSD memory card. At the end of the post, he poses the following question, “If we can build nine-stacks of 30 µm-thick dice with wire bonding, will TSVs ever become economic in the commodity chip arena?” I found this an interesting question to pose to our panel. Bob – since you’re in the memory stacking business, perhaps you’d like to respond. Read More>>
By Ed Korczynski On Jul. 09, 2009
With separate 2D roadmaps already needed for Logic, DRAM, and Flash, will divergent IC applications call for multiple 3D roadmaps (perhaps global vs. local interconnect, memory-stack vs. SoC, etc.)? Read More>>
By Francoise Von Trapp On Jul. 09, 2009
Paul, in your opinion as an equipment manufacturer, what has been delaying the implementation of 3D IC technology in high-volume manufacturing? Read More>>
By Francoise Von Trapp On Jul. 09, 2009
Welcome to the first day of the 3D Brightspots IC forum. This first round of questions across the topics is directed to all the panelists. Are standards necessary for the adoption of 3D integration schemes? Read More>>
By Francoise Von Trapp On Jul. 09, 2009
Lack of design tools has been identified as one of the current roadblocks to market adoption. Ricardo, from your perspective as a member of the design tool community, what new capabilities are required of EDA tools in order to support 3D IC design? Read More>>